The invention relates to a circuit arrangement for converting a parallel data stream into a serial data stream and for intermediate storage and clocked supply of the data stream, and for reversibly converting of a serial data stream into a parallel data stream.
In known circuit arrangements for parallel/serial conversion, a memory control is required so that a pointer indicates the stack which is to be written as the next one and a further pointer indicates a stack which is to be read as the next one. Simultaneous access to both fields is not possible. Furthermore, adaptation of such a memory arrangement to different bit frame widths is not possible, or the available memory location is not completely utilized. Due to the required sequential processing, such an arrangement is not very fast. Moreover, it requires frequent use of software, i.e. use of a processor, which in turn is a burden for the processor which must normally perform other tasks.
It is an object of the invention to provide a circuit arrangement for parallel/serial conversion as well as for serial/parallel conversion which operates as fast as possible, requires minimal software control and can be flexibly used as far as the bit frame width is concerned.
In a circuit arrangement for parallel/serial conversion, this object is solved in that a first shift register is provided in which the parallel data stream is stored in bit frames in dependence upon an externally supplied processor clock and which supplies a serial data stream by means of bit-wise scanning of the stored data, which serial data stream is applied in parallel to all memory locations of a second, bit-wise addressable shift register from which the data stored therein are serially read in dependence upon a serial clock, and which supplies the serial data stream, in that the second shift register is assigned to a load shift register supplying a level indicator which constantly marks the limit between memory cells of the second shift register with valid, stored data and memory cells which are to be newly written with data, and in that storage of the data supplied by the first shift register in the second shift register is effected in dependence upon the level indicator in such a way that a bit present in all memory cells of the second shift register and supplied by the first shift register is stored in that memory cell to be newly written with data which is most proximate to the level indicator and adjoins the memory cells written with valid data.
The circuit arrangement has a first and a second shift register as central elements. The parallel data supplied by a microprocessor in a predetermined clock are parallel written into the first shift register.
In the case of dependence of a serial clock which may be derived, for example, from this processor clock, the bits stored in the first shift register are serially scanned bit-wise, i.e. for example, the bits of a frame are consecutively and individually transmitted to the second shift register. The second shift register has memory cells which can be individually addressed for the purpose of writing. For each individual bit, it can thus be freely decided which memory cell is to be written with the bit. To take this decision, a second shift register is assigned to a load shift register which comprises a level indicator. This may be, for example, a bit which is shifted through the memory cells of the load shift register. This level indicator constantly supplies information about the location of the limit between those memory cells in the second shift register which were already validly written with bits from the first shift register, and those memory cells which may already have been written but whose contents are not yet valid. The level indicator thus also marks that memory cell which is to be written as the next one with a bit coming from the first shift register. The storage of bits coming from the first shift register is therefore performed in dependence upon this level indicator.
Reading the data from the second shift register may be effected in dependence upon a serial clock which may be basically independent of the clock with which the first shift register is loaded.
The arrangement has the specific advantage that it operates on the basis of hardware because it is only dependent on the clock signals and on the level indicator which are available anyway or are generated as hardware within the arrangement. The arrangement thus requires a minimal use of the processor so that the processor from which, for example, the parallel data originate, is relieved from this burden. Furthermore, the parallel/serial conversion constantly takes place without any interruptions because there are no waiting times which are produced in known arrangements because it is not possible to simultaneously write and read in memory areas of a memory. The limitation of the operating speed of the arrangement is not only caused by the arrangement itself but also by the speed at which the data are supplied and requested.
Claim 2 describes an advantageous embodiment of this arrangement which allows a constant update of the level indicator in the load shift register in a simple manner. To this end, a shift signal is generated by means of a counter, which signal is applied to the load shift register and the first shift register. When, in dependence upon this shift signal, a new bit is read from the first shift register and written into the next memory cell to be written of the second shift register, the level of the level indicator in the load shift register is also corrected accordingly by this signal. After writing a memory cell, the level indicator will point at the next memory cell which is to be written. Furthermore, the serial clock at which the data are serially read from the second shift register is also applied to the load shift register so as to perform, conversely, a corresponding correction of the level indicator when a bit has been read from the second shift register. In this way, a constant correction of the level indicator is effected in dependence upon whether a new bit is read or written.
The above-described advantages of the arrangement according to the invention can be further improved in that the arrangement, as defined in claim 3, is formed in such a way that it can also process the variable frame widths of the parallel bits applied thereto. To this end, the first shift register has as many memory cells as are required for a maximum bit frame width, denoted as physical bit frame width. When actually parallel bits of a smaller, so-called logic frame width are supplied, then these bits are also parallel written into the first shift register. However, gaps are then produced which initially are not written by bits. A frame logic is provided which in the case of further shifting the bits in the first shift register tracks that bit which is to be read as the next one. To render this possible, the memory cells are constructed in such a way that the bit stored in each memory cell can be individually read. When there is a clock of the shift signal, the shift register is shifted further and also the frame logic will follow in accordance with the new position of the next bit to be read. Reading of this bit is controlled by the frame logic and is parallel supplied to all memory cells of the second shift register, in which storage takes place in dependence upon the level indicator.
In a further embodiment of the invention as defined in claim 5, the arrangement supplies two signals which signalize a complete filling of the second shift register or a relatively small filling level of this shift register. An arrangement which supplies the parallel data can thereby be controlled.
In principle, the described arrangement for parallel/serial conversion may also be used in the same construction for serial/parallel conversion. To this end, the measures as defined in claim 7 are preferably taken.
Also in this mode of operation, the same advantages are obtained because a mode of operation which is substantially independent of the use of software is also guaranteed in this case and the arrangement does not require any waiting state or the like.
In this mode of operation, the serially supplied data are stored in the second shift register in dependence upon an external serial clock. They are read again bit-wise from the memory cells of this shift register, with the level indicator now signalizing that memory cell from which the next bit is to be read. This bit is written into the first shift register. This process is repeated until a bit frame width of stored bits is present in the first shift register which can then be parallel read.